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[VHDL-FPGA-Verilog] A

Description: 基于CPLD的VHDL语言数字钟(含秒表)设计及程序 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。-The VHDL language based on CPLD digital clock (including a stopwatch) design and program By using a chips in addition to clock source, buttons, the speaker and displays (digital tube) all the digital circuit function outside. All digital logic function in with VHDL language CPLD device realized. This design has small, the design cycle short (design process can be realized in the temporal simulation), convenient debug, low failure rate, modify upgrade easily etc. Characteristics.
Platform: | Size: 95232 | Author: ruohai | Hits:

[VHDL-FPGA-Verilog] watch

Description: 使用vhdl设计数码管显示的秒表； 能够准确的计时并显示； 开机显示00.00.00； 用户可以随时清零、暂停、计时；最大记时59分钟，最小精确到0.01秒。-Vhdl design digital display stopwatch accurate timing and display boot display 00.00.00 Users can be cleared at any time, suspend, timing 59 minutes maximum chronograph, accurate to 0.01 seconds minimum.
Platform: | Size: 346112 | Author: 陈小龙 | Hits:

[VHDL-FPGA-Verilog] EDAreport

Description: 用VHDL实现秒表功能，即使时间为60分钟，实验报告格式，代码在文档最后。仿真软件使用quartus2-Using VHDL stopwatch function, even if the time is 60 minutes, the test report form, the code at the end of the document. Simulation software use quartus2
Platform: | Size: 116736 | Author: hedy | Hits:

[VHDL-FPGA-Verilog] EDA

Description: VHDL实现一个整点报时的秒表第一个子程序-VHDL achieve a integral point time of the stopwatch 1
Platform: | Size: 6144 | Author: 于欣雨 | Hits:

[VHDL-FPGA-Verilog] Second_VHDL

Description: 本程序是用VHDL实现的秒表，通过对主时钟进行分频得到低速时钟，以调试通过，大家可以参考。-This program is implemented with VHDL stopwatch, low-speed clock master clock divider to debug through, we can refer to.
Platform: | Size: 45056 | Author: 工程师 | Hits:

[Other Embeded program] EDAmiaobiao

Description: 基于VHDL语言的EDA秒表作业设计，包括分频、秒表主体和数码管显示译码器，附有工程文件和管脚信息（EDA大作业西电02105143）-VHDL language based the EDA the stopwatch job design, including divide the stopwatch the main digital display decoder, with the project file and pin information (EDA Job Western Electric 02105143)
Platform: | Size: 433152 | Author: VanillaChow | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 用VHDL语言实现对FPGA的程序编写，实现秒表功能。-Using VHDL FPGA program written stopwatch function.
Platform: | Size: 372736 | Author: 秦丽媛 | Hits:

[Software Engineering] miao-biao

Description: 基于vhdl实现数字秒表，实验报告完整版，代码可直接应用-The lab report the full version of the code can be applied directly on vhdl digital stopwatch
Platform: | Size: 108544 | Author: 李雅婷 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 基于Max+plus2软件的Verilog VHDL语言的按键控制数码管显示秒表-Based on Max+plus2 software Verilog VHDL language button control digital display stopwatch
Platform: | Size: 457728 | Author: lzhf | Hits:

[VHDL-FPGA-Verilog] vhdl_miaobiao

Description: 基于FPGA，VHDL实现秒表功能，利用了分频和计数-FPGA, VHDL-based stopwatch function, the use of divide and count
Platform: | Size: 7168 | Author: ljx | Hits:

[VHDL-FPGA-Verilog] jing

Description: 用VHDL语言编程一个具有秒计时，定时的数字时钟，其中包括程序，图示，仿真结果及报告。-VHDL programming a stopwatch, digital clock timing, including procedures, icon, simulation results and reports.
Platform: | Size: 28905472 | Author: 景睿睿 | Hits:

[Other] miaobiao

Description: 利用vHdl描述语言实现的60秒秒表。能够实现60秒的计时功能-Use of vHdl description language implementation 60 seconds stopwatch
Platform: | Size: 1024 | Author: wuqiangsheng | Hits:

[VHDL-FPGA-Verilog] seconds-counter

Description: 在EP2C5T144C8开发板上编的一个VHDL源程序，相当于一个秒表，读数可在4个数码管上显示，通过按键可暂停计数，可继续计数-In EP2C5T144C8 development board this a VHDL source code, the equivalent of a stopwatch, reading on the four digital tube display, can suspend count by buttons, can continue to count
Platform: | Size: 615424 | Author: 李杰 | Hits:

[OS Develop] matlab

Description: vhdl learning materials，-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3661824 | Author: ttt | Hits:

[SCM] secnew

Description: 基于FPGA的数字秒表设计。用VHDL语言设计数字秒表。-FPGA-based design of digital stopwatch. Design using VHDL digital stopwatch.
Platform: | Size: 385024 | Author: youjiaxin | Hits:

[VHDL-FPGA-Verilog] finaldesign_watch

Description: 基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for the development, the use of the VHDL language, from 0.01 seconds to 59 minutes 59 seconds 59 design.
Platform: | Size: 985088 | Author: huyanting | Hits:

[VHDL-FPGA-Verilog] timer

Description: 基于VHDL语言的一个简单秒表，包含按键消抖模块、数码管译码、计时器等模块。直接适用于basys2和nexys3两个开发板。更改ucf文件后适用于其他开发板-A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards. After changing the ucf file applicable to other development board
Platform: | Size: 16384 | Author: 潘健森 | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 基于CPLD的智能数字时钟VHDL设计，能实现时钟、秒表、闹钟、定时等功能-ntelligent digital clock CPLD VHDL-based design enables the clock, stopwatch, alarm clock, timer, and other functions
Platform: | Size: 411648 | Author: Steve | Hits:

[VHDL-FPGA-Verilog] exp18

Description: 这是一个vhdl的交通灯程序，可以实现两个方向间红、黄、绿灯之间的亮灭转换，同时还有秒表的计数、显示功能，为学习vhdl的人提供一定的技术参考。-This is a vhdl traffic lights procedures can be achieved between the two directions of red, yellow, green light off between the conversion, as well as the stopwatch count, display, provide a technical reference for learning vhdl person.
Platform: | Size: 1024 | Author: 殷超 | Hits:

[VHDL-FPGA-Verilog] MB

Description: 基于VHDL语言数字秒表设计,在FPGA实验平台下开发-Digital stopwatch design based on VHDL, FPGA experimental platform under development
Platform: | Size: 222208 | Author: 李耀 | Hits:
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